Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link
Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link
复制标题
65nm CMOS 电感耦合链路中电源/信号线和 SRAM 电路的干扰
DOI：
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
T. Kuroda
中科院分区：
文献类型：
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作者：
K. Niitsu;Y. Sugimori;Y. Kohama;K. Osada;N. Irie;H. Ishikuro;T. Kuroda
本文讨论了65nm CMOS中电感耦合环节的干扰问题。对电源线、信号线和SRAM的电磁干扰进行了仿真和测量。移动的应用（线路和空间）的电力线干扰小于高性能应用（网格型）的电力线干扰。即使在逻辑电路的最坏情况下，来自信号线的干扰也只需要9%的额外发射功率。在典型的工作范围内，对SRAM的干扰是可以忽略的。只有当电源电压远低于典型范围时，来自电感耦合链路的位线噪声才会影响SRAM的工作。与器件变化和软错误等其他影响相比，对SRAM的干扰很小。
This paper discusses interference of an inductive-coupling link in 65nm CMOS. Electromagnetic interference from power/signal lines and to SRAM was simulated and measured. Interference from power lines for mobile applications (line and space) is smaller than that for high-performance applications (mesh type). Interference from signal lines requires only 9% of additional transmit power even in the worst case of logic circuits. In typical operation range, interference to SRAM is ignorable. Only when supply voltage is much lower than typical range, the bit-line noise from the inductive-coupling link influences SRAM operation. Interference to SRAM is small compared with other influences such as device variations and soft errors.