Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems
Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems
复制标题
使用自旋晶体管架构的非易失性延迟触发器，具有用于功率门控系统的自旋转移力矩 MTJ
DOI：
10.1049/el.2011.1807
复制
发表时间：
2011
影响因子：
1.1
通讯作者：
S. Sugahara
中科院分区：
文献类型：
--
作者：
S. Yamamoto;Y. Shuto;S. Sugahara
对作者以前提出的具有自旋转移扭矩磁隧道结(STT-MTJ)的非易失性延迟触发器(NV-DFF)的功率门控能力进行了计算分析。首次提出了衡量PG系统能量性能的重要指标--非易失性逻辑电路的盈亏平衡时间(BET)。通过对单元中伪自旋晶体管部分的设计，可以有效地降低NV-DFF的BET。NV-DFF适用于粗粒度和细粒度的PG结构，因为它在实际的CMOS逻辑应用中具有亚微秒级的潜在BET。
The power-gating (PG) ability of the authors' previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-spin-transistors with spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-spin-transistor parts of the cell. The NV-DFF is applicable to coarse- and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.