Parallel template matching operations on a dynamically reconfigurable vision-chip architecture
Parallel template matching operations on a dynamically reconfigurable vision-chip architecture
复制标题
动态可重构视觉芯片架构上的并行模板匹配操作
DOI:
10.1109/iscit.2010.5665152
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发表时间:
2010
期刊:
影响因子:
--
通讯作者:
S. Kawahito
中科院分区:
文献类型:
--
作者:
Hironari Nakada;Minoru Watanabe;S. Kawahito
Recently, high-speed image recognition functionality that is superior to the image recognition speed of the human eye is demanded for autonomous vehicles and robots. Currently, such embedded systems comprise a processor and memory. To recognize many images, many template images must be stored in memory and must be sent quickly from memory to the processor. For example, assuming that the system receives an external image with 1 million pixels at every 1 ms and assuming that the system must execute template-matching operations of 1 million template images with the same million pixels within 1 ms, then the transfer speed from the memory to the processor and the processor operation reaches 1 Petapixel/s. Therefore, to realize high-speed template-matching operation, a dynamically reconfigurable vision-chip architecture with a holographic memory and large-bandwidth optical connections has been proposed. Among such researches, this paper presents a proposal of novel parallel template-matching operations performed on the dynamically reconfigurable vision-chip architecture. Furthermore, the advantages of the new method are discussed based on some demonstration results.