A Survey of Cache Coherence Schemes for Multiprocessors
A Survey of Cache Coherence Schemes for Multiprocessors
复制标题
多处理器缓存一致性方案综述
DOI：
10.1109/2.55497
复制
发表时间：
1990
期刊：
影响因子：
2.2
通讯作者：
P. Stenström
中科院分区：
文献类型：
--
作者：
P. Stenström
研究了表现出不同程度的硬件复杂性的缓存一致性方案，从维持硬件一致性的协议到防止共享、可写数据副本存在的软件策略。研究了一些使用共享数据的示例。这些示例有助于指出许多性能问题。考虑硬件协议。可以看出，尽管在某些情况下具有相当大的硬件复杂性，特别是对于具有许多处理器的多处理器，但是可以有效地维持一致性。研究了软件方案作为能够降低硬件成本的替代方案。 >
Schemes for cache coherence that exhibit various degrees of hardware complexity, ranging from protocols that maintain coherence in hardware, to software policies that prevent the existence of copies of shared, writable data, are surveyed. Some examples of the use of shared data are examined. These examples help point out a number of performance issues. Hardware protocols are considered. It is seen that consistency can be maintained efficiently, although in some cases with considerable hardware complexity, especially for multiprocessors with many processors. Software schemes are investigated as an alternative capable of reducing the hardware cost. >