big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
复制标题
DOI:
10.1109/micro56248.2022.00025
复制
发表时间:
2022-10
期刊:
影响因子:
--
通讯作者:
T. Ta;Khalid Al-Hawaj;Nick Cebry;Yanghui Ou;Eric Hall;Courtney Golden;C. Batten
中科院分区:
文献类型:
--
作者:
T. Ta;Khalid Al-Hawaj;Nick Cebry;Yanghui Ou;Eric Hall;Courtney Golden;C. Batten
Single-ISA heterogeneous multi-core architectures offer a compelling high-performance and high-efficiency solution to executing task-parallel workloads in mobile systems on chip (SoCs). In addition to task-parallel workloads, many data-parallel applications, such as machine learning, computer vision, and data analytics, increasingly run on mobile SoCs to provide real-time user interactions. Next-generation scalable vector architectures, such as the RISC-V Vector Extension and Arm SVE, have recently emerged as unified vector abstractions for both large- and small-scale systems. In this paper, we propose novel area-efficient high-performance architectures called big.VLITTLE that support next-generation vector architectures to efficiently accelerate data-parallel workloads in conventional big.LITTLE systems. big.VLITTLE architectures reconFigure multiple little cores on demand to work as a decoupled vector engine when executing data-parallel workloads. Our results show that a big.VLITTLE system can achieve $1.6\times$ performance speedup over an area-comparable big.LITTLE system equipped with an integrated vector unit across multiple data-parallel applications and $1.7\times$ speedup compared to an aggressive decoupled vector engine for task-parallel workloads.