Synthesis of PCHB-WCHB hybrid quasi-delay insensitive circuits
Synthesis of PCHB-WCHB hybrid quasi-delay insensitive circuits
复制标题
PCHB-WCHB混合准延迟不敏感电路的综合
DOI：
10.1145/2593069.2593224
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
J. H. Jiang
中科院分区：
文献类型：
--
作者：
C. Chuang;Yi;J. H. Jiang
随着时钟集成电路成本的不断增加以及与时序变化的斗争，设计人员不得不重新考虑系统实现的异步方法。在各种技术中，准延迟不敏感（QDI）设计由于其非常宽松的时序假设而很有前途。然而，其昂贵的逻辑开销常常使其性能和功率改进的承诺落空，并且仍然是其采用的主要障碍。为了克服这一障碍，本文提出了一种有效的静态性能分析程序和预充电半缓冲器（PCHB）和弱条件半缓冲器（WCHB）电路优化的综合流程。实验结果表明，在管道循环时间约束下，有效的性能分析和有效的面积缩减。
The increasing cost paid in clocking integrated circuits and combating timing variations forces designers to rethink asynchronous approaches to system realization. Among various techniques, quasi-delay-insensitive (QDI) design is promising due to its very relaxed timing assumption. Its expensive logic overhead, however, often nullifies its promise of performance and power improvements, and remains a major obstacle against its adoption. To overcome this obstacle, this paper proposes an efficient static performance analysis procedure and a synthesis flow for precharged half buffer (PCHB) and weak-conditioned half buffer (WCHB) circuit optimization. Experimental results demonstrate efficient performance analysis and effective area reduction under pipeline cycle time constraints.