A fair comparison of adders in stochastic regime
A fair comparison of adders in stochastic regime
复制标题
随机状态下加法器的公平比较
DOI：
--
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
A. Ortiz
中科院分区：
文献类型：
--
作者：
Ardalan Najafi;M. Weißbrich;G. P. Vayá;A. Ortiz
高速和节能系统的需求导致了近似计算的出现。现有的近似电路以及随机技术在改善各种品质因数方面已经显示出有希望的进步。然而，算术单位的彻底公平比较仍然是一个尚未研究的问题。本文回顾了近似算术单位公平比较的先决条件。加法器作为运算电路的关键部件之一，是本文研究的重点。本文首次在随机状态下同时研究近似加法器和精确加法器。仿真结果表明，当且仅当选择了正确的配置和子加法器架构时，等分段加法器 (ESA) 和容错加法器 II 型 (ETAII) 的性能都优于随机工作的精确加法器。否则，没有理由使用上述架构。总而言之，考虑到成本与误差的权衡，下部或加法器 (LOA) 在随机状态下具有最佳行为。
The demands of high-speed and power-efficient systems have resulted into the emergence of the approximate computing. Existing approximate circuits as well as stochastic techniques have shown promising advances in improving various figures of merit. However, a through fair comparison of arithmetic units still remains an issue which has not been studied. This paper reviews the prerequisites for a fair comparison of approximate arithmetic units. As one of the key components of arithmetic circuits, adders are the focus of this paper. For the first time in this paper, approximate and exact adders are studied together in the stochastic regime. Simulation results show that both the equal segmentation adder (ESA) and the error tolerant adder type II (ETAII) outperform exact adders working stochastically, if and only if the right configuration and sub-adder architectures are chosen. Otherwise, there is no reason to use the aforementioned architectures. In all, considering the cost-error trade-off, Lower-part OR adder (LOA) has the best behavior in the stochastic regime.