Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
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DOI：
10.1109/fccm.2018.00029
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发表时间：
2018-04
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影响因子：
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通讯作者：
Steve Dai;Yuan Zhou;Hang Zhang;Ecenur Ustun;Evangeline F. Y. Young;Zhiru Zhang
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作者：
Steve Dai;Yuan Zhou;Hang Zhang;Ecenur Ustun;Evangeline F. Y. Young;Zhiru Zhang
虽然高级合成（HLS）提供了精致的技术来优化领域和性能的设计，但HLS估计的资源使用情况和时机通常会显着偏离FPGA键入的设计实现的实际质量质量（QOR）。不准确的HLS估计，可以防止设计人员在不诉诸于耗时的下游实现过程的情况下执行有意义的设计空间探索。为了应对这一挑战，我们首先从各种现实的HLS应用程序中构建了大量的C到FPGA结果，并从HLS报告中确定相关功能，以估算实施后指标。然后，我们利用这些功能和数据来训练和比较许多有希望的机器学习模型，以有效有效地弥合准确性差距。实验表明，我们提出的方法能够大大减少FPGA设备不同家族的估计错误。通过从我们的实验中提取域特异性见解，我们探讨了模型的含义以及各种特征对在HLS中快速准确估计的预测影响。我们已将数据集发布到该领域的Springboard未来工作。
While high-level synthesis (HLS) offers sophisticated techniques to optimize designs for area and performance, HLS-estimated resource usage and timing often deviate significantly from actual quality of results (QoR) achieved by FPGA-targeted designs. Inaccurate HLS estimates prevent designers from performing meaningful design space exploration without resorting to the time-consuming downstream implementation process. To address this challenge, we first build a large collection of C-to-FPGA results from a diverse set of realistic HLS applications and identify relevant features from HLS reports for estimating post-implementation metrics. We then leverage these features and data to train and compare a number of promising machine learning models to effectively and efficiently bridge the accuracy gap. Experiments demonstrate that our proposed approach is able to dramatically reduce the estimation errors for different families of FPGA devices. By extracting domain-specific insights from our experiments, we explore the implications of our models and predictive influence of various features for enabling fast and accurate QoR estimation in HLS. We have released our dataset to springboard future efforts in this area.