Built-in self testing of sequential circuits using precomputed test sets
Built-in self testing of sequential circuits using precomputed test sets
复制标题
使用预先计算的测试集对时序电路进行内置自测试
DOI：
--
复制
发表时间：
1998
期刊：
影响因子：
--
通讯作者：
B. Murray
中科院分区：
文献类型：
--
作者：
V. Iyengar;K. Chakrabarty;B. Murray
我们提出了一种新的方法，可以使用预先计算的测试集进行连续电路的内置自我测试。我们的方法特别适合包含大量触发器但几乎没有主要输入的电路。这些电路通常是作为嵌入式内核和用于数字信号处理的滤波器而遇到的，并且本质上很难测试。我们表明，测试集的统计编码可以与确定性剑的低成本模式解码结合使用。这种方法利用了顺序电路ATPG的最新进展，与其他BIST方案不同，不需要访问测试电路的门级模型。实验结果表明，所提出的方法与较短的测试应用时间相比，所提出的方法比伪随机测试提供了更高的故障覆盖率。
We present a new approach to built-in self-test of sequential circuits using precomputed test sets. Our approach is especially suited to circuits containing a large number of flip-flops but few primary inputs. Such circuits are often encountered as embedded cores and filters for digital signal processing, and are inherently difficult to test. We show that statistical encoding of test sets can be combined with low-cost pattern decoding for deterministic BIST. This approach exploits recent advances in sequential circuit ATPG and unlike other BIST schemes, does not require access to gate-level models of the circuit under test. Experimental results show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time.