Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures
复制标题
减少 NISQ 架构上 Clifford T 电路的 CNOT 计数
DOI：
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发表时间：
2020
影响因子：
2.9
通讯作者：
Priyanka Mukhopadhyay
中科院分区：
文献类型：
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作者：
Vlad Gheorghiu;Jiaxin Huang;Sarah Meng Li;M. Mosca;Priyanka Mukhopadhyay
将量子电路映射到物理层时，必须考虑底层硬件架构所施加的众多限制。物理量子位的连接性就是这样一种约束，它将两个量子位操作（例如 CNOT）限制为“连接”的量子位。交换门可用于将逻辑量子位放置在可接受的物理量子位上，但它们会导致 CNOT 计数显着增加。在本文中，我们考虑减少连接受限架构上 Clifford+T 电路中 CNOT 计数的问题，例如噪声中等规模量子 (NISQ) 计算设备。我们在 Hadamard 门的位置对电路进行“切片”，并使用 Steiner 树“构建”中间 ${ ext {CNOT},{T}}$ 子电路，显着改进了以前的方法。我们比较了算法的性能，同时将不同的基准和随机电路映射到一些著名的架构，例如 9 量子位方形网格、16 量子位方形网格、Rigetti 16 量子位 Aspen、16 量子位 IBM QX5 和 20 量子位 IBM Tokyo。与 Qiskit 和 TKET 转译器以及使用 SWAP 门相比，我们的方法给出的 CNOT 计数更少。假设 NISQ 电路实现中的大多数错误都是由于 CNOT 错误造成的，那么我们的方法将允许可靠地实现比以前的方法所允许的 CNOT 门多几倍的电路。
While mapping a quantum circuit to the physical layer one has to consider the numerous constraints imposed by the underlying hardware architecture. Connectivity of the physical qubits is one such constraint that restricts two-qubit operations, such as CNOT, to “connected” qubits. SWAP gates can be used to place the logical qubits on admissible physical qubits, but they entail a significant increase in CNOT-count. In this article, we consider the problem of reducing the CNOT-count in Clifford+T circuits on connectivity-constrained architectures, like noisy intermediate-scale quantum (NISQ) computing devices. We “slice” the circuit at the position of Hadamard gates and “build” the intermediate ${ ext {CNOT},{T}}$ subcircuits using Steiner trees, significantly improving on previous methods. We compared the performance of our algorithms while mapping different benchmark and random circuits to some well-known architectures, such as 9-qubit square grid, 16-qubit square grid, Rigetti 16-qubit Aspen, 16-qubit IBM QX5, and 20-qubit IBM Tokyo. Our methods give less CNOT-count compared to Qiskit and TKET transpiler as well as using SWAP gates. Assuming most of the errors in an NISQ circuit implementation are due to CNOT errors, then our method would allow circuits with a few times more CNOT gates be reliably implemented than the previous methods would permit.
影响因子：
6.4
作者：
Preskill, John
通讯作者：
Preskill, John