APRON: A Cellular Processor Array Simulation and Hardware Design Tool
APRON: A Cellular Processor Array Simulation and Hardware Design Tool
复制标题
APRON：蜂窝处理器阵列仿真和硬件设计工具
DOI：
10.1155/2009/751687
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发表时间：
2009
影响因子：
1.9
通讯作者：
P. Dudek
中科院分区：
文献类型：
--
作者：
D. Barr;P. Dudek
我们提出了一个软件环境，用于有效模拟蜂窝处理器阵列（CPA）。该软件（围裙）用于探索专为大规模平行的细粒处理器阵列，地形多层神经网络，带SIMD处理器阵列的视觉芯片以及相关架构设计而设计的算法。该软件使用高度优化的核心与灵活的编译器相结合，为用户提供用于设计新处理器阵列硬件体系结构和现有设备的工具。我们为在标准商品微处理器上实施的软件处理器阵列提供了性能基准。可以在必要时配置围裙以使用其他处理硬件，并可以用作新的或现有CPA系统的完整图形用户界面和开发环境，从而使更多用户可以为CPA系统开发算法。
We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.