Total cost effective scallop free Si etching for 2.5D & 3D TSV fabrication technologies in 300mm wafer
Total cost effective scallop free Si etching for 2.5D & 3D TSV fabrication technologies in 300mm wafer
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总体成本效益高的 2.5D 无扇贝硅蚀刻
DOI：
10.1109/ectc.2013.6575636
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
K. Suu
中科院分区：
文献类型：
--
作者：
Y. Morikawa;T. Murayama;Yuu Nakamuta Toshiyuki Sakuishi;A. Suzuki;K. Suu
近年来，高性能LSI的“2.5D硅中间层”和“全3D堆叠”技术备受关注，因为该技术可以解决使用TSV （Through silicon Via）电连接堆叠LSI的互连问题。与传统的2D器件相比，2.5D和3D Si集成具有封装密度高、线长小、运行速度快、功耗低、并行处理可行性高等优点。但是，TSV生产成本的根本问题仍然没有得到解决。特别是，预计需要一种新的镀液技术来缩短镀铜时间。另一方面，成本较低的高频器件TSV隔离衬垫材料在未来将是必要的。“无扇贝”蚀刻工艺被开发用于TSV制造[1]。同时，光滑的侧壁也缩短了PVD工艺时间。本文首先研究了锥形蚀刻与Cu-ECP（电化学镀）的成本相关性。然后，采用气相沉积聚合技术（Ulvac的FPF/PV大面板技术）的聚脲膜尝试作为下一代高频设备的隔离衬里。并且，它将薄膜形成为TSV模式。
In recent years, "2.5D silicon interposers" and "Full 3D stacked" technology for high-performance LSI has attracted much attention since this technology can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked LSI. 2.5D and 3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the TSV production cost is not still solved. In particular, the demand to a new plating bath technology to shorten Cu plating time is expected. On the other hand, TSV isolation liner materials with lower cost for high frequency devices will be necessary in future. “Scallop-free” etching process has developed for TSV fabrication [1]. And, the smooth-sidewall had proved shorten PVD process time [2]. At first, it investigated a cost correlation of taper-shape etching and Cu-ECP (electrochemical plating) in this paper. And then, a polyurea film using a vapor deposition polymerization technology (which is Ulvac's FPF/PV large panel technology) tried introduction as isolation liner for next-generation high frequency device. And, it performed the film formation to a TSV pattern.