An FPGA architecture for DRAM-based systolic computations
An FPGA architecture for DRAM-based systolic computations
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用于基于 DRAM 的脉动计算的 FPGA 架构
DOI：
10.1109/fpga.1997.624599
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发表时间：
1997
期刊：
影响因子：
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通讯作者：
N. Margolus
中科院分区：
文献类型：
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作者：
N. Margolus
我们根据常规的FPGA逻辑数组核心提出了一个FPGA芯片架构，其中I/O引脚的速率比它们所使用的逻辑数组的速率要高得多。芯片内的宽数据路径是在芯片边缘多路复用的时间，使其更快，更狭窄的数据路径运行片段。这种安排使得可以使用高速记忆和数据流相对较慢的FPGA核心将其连接起来，并且对于许多PIN限制的FPGA应用程序很有用。为了有效利用最高的带宽DRAM，我们提出的芯片包括Rambus DRAM接口，突发转移控制器和爆发缓冲区。该建议是由我们使用虚拟处理器蜂窝自动机（CA）机器的工作来激发的。我们的下一代CA机需要可重新配置的类似FPGA的处理器，并耦合到可用的最高速度DRAM和SRAM。不幸的是，没有当前的FPGA芯片具有适当的DRAM I/O支持，或者很容易与管道的SRAM接口所需的速度。提议的芯片将对3D物理系统实用和经济模拟进行广泛的大规模CA模拟，这些模拟目前远远超出了任何现有计算机的范围。这些芯片也将非常适合多种其他模拟，图形和类似DSP的应用。
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serve. Wide data paths within the chip are time multiplexed at the edge of the chip into much faster and narrower data paths that run off-chip. This kind of arrangement makes it possible to interface a relatively slow FPGA core with high speed memories and data streams, and is useful for many pin-limited FPGA applications. For efficient use of the highest bandwidth DRAMs, our proposed chip includes a RAMBUS DRAM interface, a burst-transfer controller, and burst buffers. This proposal is motivated by our work with virtual processor cellular automata (CA) machines-a kind of SIMD computer. Our next generation of CA machines requires reconfigurable FPGA-like processors coupled to the highest speed DRAMs and SRAMs available. Unfortunately, no current FPGA chips have appropriate DRAM I/O support or the speed needed to easily interface with pipelined SRAMs. The chips proposed would make a wide range of large-scale CA simulations of 3D physical systems practical and economical-simulations that are currently well beyond the reach of any existing computer. These chips would also be well suited to a broad range of other simulation, graphics and DSP-like applications.