Logic optimization for majority gate-based nanoelectronic circuits
Logic optimization for majority gate-based nanoelectronic circuits
复制标题
基于多数门的纳米电子电路的逻辑优化
DOI：
10.1109/iscas.2006.1692833
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
Wei Wang
中科院分区：
文献类型：
--
作者：
Zhi Huo;Qishan Zhang;S. Haruehanroengra;Wei Wang
在本文中，提出了一种有效的多数逻辑优化器来综合基于多数门的纳米电子电路。提出了一种新的共享和映射方案，以实现简单的综合电路和高的综合速度。实验结果表明，与现有方法相比，该方法的门数减少了20%，综合速度提高了25%。该优化器可广泛应用于量子元胞自动机、隧穿相位逻辑和单电子隧穿电路设计中
In this paper, an efficient majority logic optimizer is proposed to synthesize majority gate-based nanoelectronic circuits. A novel sharing and mapping scheme is proposed to achieve simple synthesized circuits and high synthesis speed. The experimental results show that compared to the existing method, the proposed method achieves up to 20% reduction of gate counts and 25% higher synthesis speed. This proposed optimizer can be widely used in quantum cellular automata, tunneling phase logic, and single electron tunneling circuit design