SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
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DOI：
10.1088/1748-0221/12/04/c04008
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发表时间：
2017-04
影响因子：
1.3
通讯作者：
J. Adolfsson;A. A. Pabón-A.;M. Bregant;C. Britton;G. Brulin;D. Carvalho;V. Chambert;D. Chinellato;B. Espagnon;H. Herrera;T. Ljubičić;S. Mahmood;U. Mjörnmark;D. Moraes;M. Munhoz;G. Noël;A. Oskarsson;L. Osterman;A. Pilyar;K. Read;A. Ruette;P. Russo;B. Sanches;L. Severo;D. Silvermyr;C. Suire;G. Tambave;K.M.M. Tun-Lanoë;W. Noije;A. Velure;S. Vereschagin;E. Wanlin;T. Weber;S. Zaporozhets
中科院分区：
文献类型：
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作者：
J. Adolfsson;A. A. Pabón-A.;M. Bregant;C. Britton;G. Brulin;D. Carvalho;V. Chambert;D. Chinellato;B. Espagnon;H. Herrera;T. Ljubičić;S. Mahmood;U. Mjörnmark;D. Moraes;M. Munhoz;G. Noël;A. Oskarsson;L. Osterman;A. Pilyar;K. Read;A. Ruette;P. Russo;B. Sanches;L. Severo;D. Silvermyr;C. Suire;G. Tambave;K.M.M. Tun-Lanoë;W. Noije;A. Velure;S. Vereschagin;E. Wanlin;T. Weber;S. Zaporozhets
本文介绍了为ALICE时间投影室（TPC）和μ子室（MCH）读出前端电子器件升级而设计的专用集成电路SAMPA第二原型的测试结果。SAMPA采用130 nm CMOS技术制造，标称电压为1.25 V，提供32个通道，可选择输入极性，以及三种整形时间和灵敏度组合。每个通道由一个电荷敏感放大器、一个半高斯整形器和一个10位ADC组成；数字信号处理器提供数字滤波和压缩能力。在第二次原型运行中，制造了完整的芯片和单个测试块，允许块表征和完整的系统行为研究。实验结果在这里给出了显示符合要求的两个模块和整个芯片。
This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.