Instruction-driven timing CPU model for efficient embedded software development using OVP
Instruction-driven timing CPU model for efficient embedded software development using OVP
复制标题
使用 OVP 进行高效嵌入式软件开发的指令驱动时序 CPU 模型
DOI：
10.1109/icecs.2013.6815549
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
G. Sassatelli
中科院分区：
文献类型：
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作者：
Felipe Rosa;Luciano Ost;R. Reis;G. Sassatelli
MPSoC 的软件复杂性急剧增加，带来了新的设计挑战，例如通过移植并行编程 API 来提高系统性能和可编程性。这些挑战给系统的软件开发带来了更多的时间和成本。这导致采用旨在功能验证的虚拟平台框架（例如 OVP），能够模拟以数百 MIPS 的速度运行真实应用程序代码的嵌入式系统。这项工作的重点是通过包含准周期精确定时 CPU 模型来增强 OVP 能力，使其适合性能分析。本文还评估了所提出的定时 CPU 模型与实际系统相比的准确性。结果表明，我们的模型的准确度在 0.06% 到 10.56% 之间变化，具体取决于基准配置文件。
The software complexity of MPSoCs is increasing dramatically, resulting in new design challenges, such as improving the system's performance and programmability by porting parallel programming APIs. Such challenges impose more time and cost on the system's software development. This leads to the adopting of virtual platform frameworks aimed at functional verification like OVP, capable of simulating embedded systems running real application code at the speed of hundreds of MIPS. This work focuses on enhancing OVP capability by including a quasi-cycle accurate timing CPU model, making it suitable for performance analysis. This paper also evaluates the accuracy of the proposed timing CPU model when compared to a real system. Results show that the accuracy of our model varies from 0.06% to 10.56% depending on the benchmark profile.