Parameter biasing obfuscation for analog IP protection
Parameter biasing obfuscation for analog IP protection
复制标题
用于模拟 IP 保护的参数偏置混淆
DOI：
10.1109/hst.2017.7951825
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
I. Savidis
中科院分区：
文献类型：
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作者：
Vaibhav Venugopal Rao;I. Savidis
一个独特的基于密钥的技术，混淆了模拟电路的临界偏置条件的开发。所提出的技术针对用于设置最佳偏置条件的晶体管的物理尺寸。晶体管的宽度被混淆，并且基于所应用的键序列，提供一系列潜在的偏置点。仅当应用正确的键序列时，某些晶体管才有效，并且在目标节点处设置正确的偏置点。提出的偏置加密技术是在一个标准的180 nm CMOS工艺的VCO为基础的锁相环（PLL）上实现的。电路参数，包括建立时间，功率和相位噪声的混淆和未混淆的PLL进行了比较。使用40位加密密钥来混淆偏置参数，显著提高了模拟IC的安全性。模糊PLL会导致面积增加6.3%，功耗增加0.89%，相位噪声增加5 dBc/Hz。通过暴力破解确定正确密钥的概率为9.095×10−13。通过在集成电路中的多个模拟组件上实现所提出的技术，增加了密钥空间，并且进一步提高了整体安全性。模拟混淆技术补充了现有的数字加密技术，是防止IP盗窃、伪造和模拟和混合信号电路生产过剩的有效对策。
A unique key-based technique that obfuscates the critical biasing conditions of an analog circuit is developed. The proposed technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The width of a transistor is obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied, certain transistor(s) are active, and the correct biasing points are set at the target node. The proposed bias encryption technique is implemented on a VCO based phase locked loop (PLL) in a standard 180nm CMOS process. Circuit parameters including the settling time, power, and phase noise for both the obfuscated and an un-obfuscated PLL are compared. A 40-bit encryption key is used to obfuscate biasing parameters, significantly improving the security of an analog IC. Obfuscating the PLL results in a 6.3% increase in area, 0.89% increase in power consumption, and 5 dBc/Hz increase in phase noise. The probability to determine the correct key through brute force attack is 9.095×10−13. By implementing the proposed technique on multiple analog components in the integrated circuit, the key space is increased and the overall security is further improved. The analog obfuscation technique complements existing digital encryption techniques and is an effective countermeasure against IP theft, counterfeiting, and overproduction of analog and mixed signal circuits.