Software Compartmentalization Trade-Offs with Hardware Capabilities

Software Compartmentalization Trade-Offs with Hardware Capabilities
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软件划分与硬件功能的权衡

DOI:
10.1145/3623759.3624550
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发表时间:
2023
期刊:
--
影响因子:
--
通讯作者:
Kressel J
Kressel J
中科院分区:
--
文献类型:
--
作者:
Kressel J

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划分是一种防御性软件设计形式,其中应用程序被分解为隔离但可通信的组件。从工程工作量和性能开销的角度来看,将划分改造到现有应用程序中通常被认为是昂贵的。尽管如此,近年来已经看到了划分方法的建议,这些方法承诺降低工程工作量和降低性能影响。ARM Morello将现代ARM处理器与能力硬件增强RISC指令(CHERI)的实现相结合,旨在提供高效和安全的划分。过去的作品探索基于CHERI的划分仅限于仿真/FPGA原型。在本文中,我们探讨了可能的划分方案与CHERI的Morello芯片。我们提出了两种方法,代表不同的权衡工程工作,安全性,可扩展性和性能的影响。我们描述和实现这些方法的原型操作系统上运行的裸金属的Morello芯片,划分两个流行的应用程序,并调查的性能开销。此外,我们表明,分区可以实现的工程成本,可以是相当低的,如果一个人愿意权衡的可扩展性和安全性,性能开销是类似于其他内部地址空间隔离机制。
Compartmentalization is a form of defensive software design in which an application is broken down into isolated but communicating components. Retrofitting compartmentalization into existing applications is often thought to be expensive from the engineering effort and performance overhead points of view. Still, recent years have seen proposals of compartmentalization methods with promises of low engineering efforts and reduced performance impact. ARM Morello combines a modern ARM processor with an implementation of Capability Hardware Enhanced RISC Instructions (CHERI) aiming to provide efficient and secure compartmentalization. Past works exploring CHERI-based compartmentalization were restricted to emulated/FPGA prototypes.In this paper, we explore possible compartmentalization schemes with CHERI on the Morello chip. We propose two approaches representing different trade-offs in terms of engineering effort, security, scalability, and performance impact. We describe and implement these approaches on a prototype OS running bare metal on the Morello chip, compartmentalize two popular applications, and investigate the performance overheads. Furthermore, we show that compartmentalization can be achieved with an engineering cost that can be quite low if one is willing to trade off on scalability and security, and that performance overheads are similar to other intra-address space isolation mechanisms.
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