Development of a front-end ASIC for silicon-strip detectors of the J-PARC muon g-2/EDM experiment
Development of a front-end ASIC for silicon-strip detectors of the J-PARC muon g-2/EDM experiment
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开发用于 J-PARC muon g-2/EDM 实验硅条探测器的前端 ASIC
DOI：
10.1016/j.nima.2020.164035
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
Yoshioka Tamaki
中科院分区：
文献类型：
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作者：
Sato Yutaro;Fujita Yowichi;Hamada Eitaro;Kishishita Tetsuichi;Mibe Tsutomu;Sasaki Osamu;Shoji Masayoshi;Suehara Taikan;Tanaka Manobu;Tojo Junji;Tsutsumi Tuki;Yamanaka Takashi;Yoshioka Tamaki
J-PARC μ子g− 2/EDM实验的硅条探测器需要一个具有高速率能力和深存储缓冲器的前端专用集成电路（ASIC）。在这个实验中，我们用硅条探测器从μ子衰变中重建了正电子径迹，并精确测量了μ子的反常磁矩和电偶极矩，以探索标准模型之外的新物理。前端ASIC需要容忍每条1.4 MHz的命中率，从测量开始到结束对命中率变化的稳定性为150倍，并具有40 μ s的深度存储器，时间分辨率为5 ns。为了满足实验要求，我们采用Silterra 180 nm CMOS工艺设计了一个原型ASIC“SliT 128 B”。我们报告的设计和性能的SlIT 128 B。
A front-end application specific integrated circuit (ASIC) with high rate capability and deep memory buffer is needed for the silicon-strip detector for the J-PARC muon g− 2/EDM experiment. In this experiment, we reconstruct a positron track from muon decay by the silicon-strip detector and measure the muon anomalous magnetic moment and the electric dipole moment precisely to explore new physics beyond the Standard Model. The front-end ASIC is required to tolerate hit rates of 1.4 MHz per strip, to be stable to the change of hit rate by a factor of 150 from the beginning to the end of the measurement, and to have deep memory for the period of 40 μ s with 5 ns time resolution. To satisfy the experimental requirements, we designed a prototype ASIC “SliT128B” with the Silterra 180 nm CMOS technology. We report on the design and the performance of the SliT128B.