Yosys-A Free Verilog Synthesis Suite
Yosys-A Free Verilog Synthesis Suite
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Yosys-A 免费 Verilog 综合套件
DOI：
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发表时间：
2013
期刊：
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通讯作者：
J. Kepler
中科院分区：
文献类型：
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作者：
C. Wolf;J. Glaser;J. Kepler
当今的大多数数字设计工作都是使用硬件说明语言（例如Verilog HDL或VHDL）完成的。 HDL合成用于将该HDL代码转换为数字电路。 Yosys是第一个用于Verilog HDL合成的免费开源软件，它支持绝大多数合成的Verilog功能。 Yosys是作为可扩展的框架构建的，因此可以轻松地用作自定义合成流的基础，以及用于实施和研究新合成算法的环境。 Yosys特别强调了对Rogigrgrain Logic的支持，这是诸如FPGA中逻辑映射到DSP单元格或合成的算法的理想之选，用于自定义的粗粒可重新配置硬件。 Yosys对Verilog HDL具有成熟的支持，并能够合成复杂的现实世界Verilog设计。提出和讨论了细粒和粗粒结构的示例设计流。当Yosys用作新算法的参考实施而不是封闭源替代方案时，在自由开源许可下的Yosys可以大大提高科学出版物的可重复性。
Most of todays digital design work is done using hardware description languages such as Verilog HDL or VHDL. HDL synthesis is used to translate that HDL code to digital circuits. Yosys is the first free and open source software for Verilog HDL synthesis which supports the vast majority of synthesizable Verilog features. Yosys is built as an extensible framework so it can be used easily as basis for custom synthesis flows and as environment for the implementation and research on new synthesis algorithms. Yosys has special emphasis on support for coarsegrain logic, making it ideal for algorithms such as logic mapping to DSP cells in FPGAs or synthesis for custom coarse-grain reconfigurable hardware. Yosys has mature support for Verilog HDL and is able to synthesize complex real-world Verilog designs. Example design flows for fine-grain and coarse-grain architectures are presented and discussed. The availability of Yosys under a liberal open source license can greatly improve reproducibility of scientific publications, when Yosys is used as basis for reference implementations of new algorithms instead of closed-source alternatives.