Enhanced low-power high-speed adder for error-tolerant application
Enhanced low-power high-speed adder for error-tolerant application
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DOI：
10.1109/socdc.2010.5682905
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发表时间：
2009-12
期刊：
影响因子：
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通讯作者：
Ning Zhu;W. Goh;G. Wang;K. Yeo
中科院分区：
文献类型：
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作者：
Ning Zhu;W. Goh;G. Wang;K. Yeo
当器件接近100 nm以下时，功耗和速度性能之间的权衡已成为主要的设计考虑因素。当处理大数据集时，这一点尤其重要，因此系统在功率和速度方面会降级。如果应用程序可以接受一些错误，即应用程序是容错的（ET），则可以同时实现功率的大幅降低和速度的提高。在本文中，我们将提出一种新的低功耗和高速容错加法器IV型设计称为ETAIV。所提出的ETAIV是我们早期设计ETAII [1]在速度和精度方面的增强。
The tradeoff between power consumption and speed performance has become a major design consideration when devices approach the sub-100 nm regime. It is especially critical when dealing with large data set, whereby the system is degraded in terms of power and speed. If the application can accept some errors, i.e. the application is Error — tolerant (ET), a large reduction in power and an increased in speed can be simultaneously achieved. In this paper, we shall present a novel low-power and high-speed Error-Tolerant Adder Type IV design called ETAIV. The proposed ETAIV is an enhancement of our earlier design, ETAII [1] in terms of speed and accuracy.