Addressing thermal and power delivery bottlenecks in 3D circuits
Addressing thermal and power delivery bottlenecks in 3D circuits
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DOI：
10.1109/aspdac.2009.4796518
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发表时间：
2009-01
期刊：
影响因子：
--
通讯作者：
S. Sapatnekar
中科院分区：
文献类型：
--
作者：
S. Sapatnekar
The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design. This has ramifications on two critical issues: firstly, it means that more heat is generated per unit footprint, potentially leading to thermal problems, and secondly, more current must be supplied per package pin, leading to possible power delivery bottlenecks. This paper presents an overview of the challenges and solutions in the domain of addressing these two issues in 3D integrated circuits.
