2.6 A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems
2.6 A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems
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2.6 基于内存处理方法的 2 ×30k 旋转多芯片可扩展退火处理器，用于解决大规模组合优化问题
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发表时间：
2019
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通讯作者：
M. Yamaoka
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作者：
Takashi Takemoto;Masato Hayashi;C. Yoshimura;M. Yamaoka
过去十年在一种新的计算机架构（通常称为退火处理器）的发展方面取得了令人瞩目的进展[1,2]。退火处理器为寻找伊辛模型的基态提供了一种快速方法；因此，它能够高效地解决NP难的组合优化问题[3]。除了基于超导电路的量子退火器[1]，基于CMOS技术的退火处理器也受到了越来越多的关注，并且正在模拟退火（SA）的基础上进行开发[2]。然而，这些CMOS退火处理器（CMOS - APs）仍有改进的空间，例如：i）扩大系数的位宽，ii）增加处理器处理的自旋数量。为了应对这些挑战，一种基于内存处理方法（CMOS电路和静态随机存取存储器紧密耦合[4]）的CMOS - AP已经被开发出来。它具有三个关键特性：一个自旋算子（处理本地存储器），它能提供可扩展位宽的系数，并根据吉布斯分布进行快速并行自旋更新；一个连接两个伊辛芯片的低延迟芯片间接口（I/F），从而增加了自旋数量；以及一个高度集成的自旋电路，它将自旋算子与静态随机存取存储器单元直接相连。安装在一个$2×30$k自旋系统中，该CMOS - AP展示了多芯片运行的能力，其能效比在CPU上运行模拟退火高$1.75×10^{5}$倍。
The last decade has seen impressive progress in the development of a new computer architecture, commonly known as annealing processor [1, 2]. An annealing processor provides a fast means for finding the ground state of an Ising model; thus, it can efficiently solve NP-hard combinatorial optimization problems [3]. In addition to quantum annealers based on superconducting circuits [1], annealing processors based on CMOS technology have received increased interest and are being developed on the basis of simulated annealing (SA) [2]. However, these CMOS annealing processors (CMOS-APs) have room for improvement, such as: i) expanding the bit widths of coefficients, and ii) increasing the number of spins handled by the processor. To address these challenges, a CMOS-AP based on the processing-in-memory approach (where CMOS circuits and an SRAM are tightly coupled [4]) has been developed. Its key features are threefold: a spin operator (processing local memory) which provides coefficients with expandable bit width and fast parallel spin updates according to the Gibbs distribution; a low-latency inter-chip interface (I/F) connecting two Ising chips, resulting in an increased number of spins; and a highly integrated spin circuit which directly connects the spin operator with the SRAM cell. Installed in a $2 imes30$ k spin system, the CMOS-AP demonstrates the capability for multi-chip operation with energy efficiency $1.75 imes10^{5}$ higher than running SA on a CPU.