A flexible ASIP architecture for connected components labeling in embedded vision applications
A flexible ASIP architecture for connected components labeling in embedded vision applications
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用于嵌入式视觉应用中连接组件标记的灵活 ASIP 架构
DOI：
10.7873/date.2014.367
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Tamon Sadasue
中科院分区：
文献类型：
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作者：
Juan Fernando Eusse Giraldo;R. Leupers;G. Ascheid;Patrick Sudowe;B. Leibe;Tamon Sadasue
实时识别大（例如，FullHD）帧中的像素的连接区域在许多计算机视觉应用中是强制性的且昂贵的步骤，所述计算机视觉应用在诸如智能电话、平板电脑和头戴式设备的嵌入式移动的设备中变得越来越流行。标准的现成的嵌入式处理器还不能科普这些应用所需的性能/灵活性权衡。因此，在这项工作中，我们提出了一个专用指令集处理器（ASIP）量身定制，同时执行阈值，连接组件标记和基本特征提取的图像帧。所提出的架构能够科普从QCIF到FullHD帧的帧复杂度，每像素格式为1到4字节，同时实现30帧每秒（fps）的平均帧速率。针对标准65 nm CMOS库进行了综合，获得了350 MHz的工作频率和2.1mm2的面积。此外，还对典型数据集和综合数据集进行了评价，以全面评估可实现的业绩。最后，一个完整的平面标记为基础的增强现实应用程序的开发和模拟的ASIP。
Real-time identification of connected regions of pixels in large (e.g. FullHD) frames is a mandatory and expensive step in many computer vision applications that are becoming increasingly popular in embedded mobile devices such as smart-phones, tablets and head mounted devices. Standard off-the-shelf embedded processors are not yet able to cope with the performance/flexibility trade-offs required by such applications. Therefore, in this work we present an Application Specific Instruction Set Processor (ASIP) tailored to concurrently execute thresholding, connected components labeling and basic feature extraction of image frames. The proposed architecture is capable to cope with frame complexities ranging from QCIF to FullHD frames with 1 to 4 bytes-per-pixel formats, while achieving an average frame rate of 30 frames-per-second (fps). Synthesis was performed for a standard 65nm CMOS library, obtaining an operating frequency of 350MHz and 2.1mm2 area. Moreover, evaluations were conducted both on typical and synthetic data sets, in order to thoroughly assess the achievable performance. Finally, an entire planar-marker based augmented reality application was developed and simulated for the ASIP.