High Signal Integrity Transmission Line Using Microchip Capacitors and its Design Methodology
High Signal Integrity Transmission Line Using Microchip Capacitors and its Design Methodology
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DOI：
10.1109/estc.2018.8546390
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发表时间：
2018-09
期刊：
影响因子：
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通讯作者：
Shumpei Matsuoka;M. Yasunaga
中科院分区：
文献类型：
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作者：
Shumpei Matsuoka;M. Yasunaga
在GHz域的高速数据传输中，如PCIe（Gen.5）和USB 5.0，由于印刷电路板（PCB）中的过孔和/或通孔或其他小的寄生元件引起的轻微阻抗失配会导致信号完整性（SI）的严重恶化。随着频率的增加，使用传统的阻抗匹配技术来保证SI变得几乎不可能。为了克服这个问题，我们提出了一种新型的高信号完整性传输线结构，称为“电容分段传输线（C-STL）”。C-STL是一种新型的信号完整性改善技术，它利用的不是特性阻抗匹配，而是失配。在C-STL中，我们使用嵌入迹线下方PCB中的小型微芯片电容器，并将电容器引起的有意反射叠加到目标失真信号波上，以将其恢复为理想波形。在本文中，我们还提出了C-STL的设计方法，并证明其有效性，使用模拟和原型测量。
In the high-speed data transmissions in GHz domain,such as PCIe (Gen.5) and USB 5.0, slight impedance mismatching caused by via-holes and/or through-holes, or other small parasiticelements in the traces in printed circuit board (PCBs) causes serious deterioration of signal integrity (SI). And it is becoming next to impossible to ensure the SI by using the conventional impedance matching techniques as the frequency increases. In order toovercome this problem, we propose a novel high signal integrity transmission line structure called “Capacitor Segmental Transmission Line (C-STL)”. The C-STL is a novel signal integrity improving technique that makes use of not the characteristic impedance matching but the mismatching. In the C- STL, we use small microchip capacitors embedded in the PCB under the trace, and superpose the intentional reflections,which cause from the capacitors, onto the target distorted signal waves to restore them to ideal waveforms. In this paper, we also propose the design methodology of the C-STL and demonstrate its effectiveness using simulations and prototype measurements.