SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM
SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM
复制标题
DOI：
10.1145/3579371.3589054
复制
发表时间：
2023-06
期刊：
影响因子：
--
通讯作者：
Gerasimos Gerogiannis;Serif Yesil;Damitha Sandeepa Lenadora;Dingyuan Cao;Charith Mendis;J. Torrellas
中科院分区：
文献类型：
--
作者：
Gerasimos Gerogiannis;Serif Yesil;Damitha Sandeepa Lenadora;Dingyuan Cao;Charith Mendis;J. Torrellas
稀疏矩阵密集矩阵乘法（SPMM）和采样致密矩阵密集矩阵乘法（SDDMM）内核的广泛使用使它们成为硬件加速度的候选者。但是，这些内核的加速器设计面临两个主要挑战：（1）CPU和加速器之间移动数据的开销（通常包括来自CPU的虚拟地址的地址空间转换）和（2）边际灵活性利用不同的稀疏稀疏的事实输入矩阵受益于SPMM和SDDMM算法的不同变化。为了应对这些挑战，本文提出了Spade，这是新的SPMM和SDDMM硬件加速器。 Spade通过将加速器处理元件（PES）与多核心的核心紧密耦合加速器处理元件（PES）避免了数据传输，就好像加速器PES是高级功能单元一样 - 允许加速器重复使用CPU存储器系统及其虚拟地址。 Spade通过支持基于瓷砖的ISA来达到灵活性和可编程性，足以消除提取和解码细粒说明的开销。为了证明Spade概念，我们已经绘制了简化的Spade芯片。此外，对具有224--1792 PES的Spade系统的模拟显示出其高性能和可扩展性。一个224-PE Spade系统平均比56核CPU，服务器级GPU和SPMM加速器快2.3倍，1.3倍和2.5倍，而无需考虑主机加速器数据传输的头顶。如果考虑到这样的开销，则224-PE铲系统平均比GPU和加速器快43.4倍和52.4倍。此外，Spade的面积很小和电源足迹。
The widespread use of Sparse Matrix Dense Matrix Multiplication (SpMM) and Sampled Dense Matrix Dense Matrix Multiplication (SDDMM) kernels makes them candidates for hardware acceleration. However, accelerator design for these kernels faces two main challenges: (1) the overhead of moving data between CPU and accelerator (often including an address space conversion from the CPU's virtual addresses) and (2) marginal flexibility to leverage the fact that different sparse input matrices benefit from different variations of the SpMM and SDDMM algorithms. To address these challenges, this paper proposes SPADE, a new SpMM and SDDMM hardware accelerator. SPADE avoids data transfers by tightly-coupling accelerator processing elements (PEs) with the cores of a multicore, as if the accelerator PEs were advanced functional units---allowing the accelerator to reuse the CPU memory system and its virtual addresses. SPADE attains flexibility and programmability by supporting a tile-based ISA---high level enough to eliminate the overhead of fetching and decoding fine-grained instructions. To prove the SPADE concept, we have taped-out a simplified SPADE chip. Further, simulations of a SPADE system with 224--1792 PEs show its high performance and scalability. A 224-PE SPADE system is on average 2.3x, 1.3x and 2.5x faster than a 56-core CPU, a server-class GPU, and an SpMM accelerator, respectively, without accounting for the host-accelerator data transfer overhead. If such overhead is taken into account, the 224-PE SPADE system is on average 43.4x and 52.4x faster than the GPU and the accelerator, respectively. Further, SPADE has a small area and power footprint.