Area- and throughput-optimized VLSI architecture of sphere decoding
Area- and throughput-optimized VLSI architecture of sphere decoding
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面积和吞吐量优化的球形解码 VLSI 架构
DOI：
10.1109/vlsisoc.2010.5642593
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
Christoph Studer
中科院分区：
文献类型：
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作者：
M. Wenk;L. Bruderer;A. Burg;Christoph Studer
球面解码（SD）是在多输入多输出（MIMO）无线通信系统中实现高性能数据检测的一种很有前途的方法。在本文中，我们重点研究了具有最小区域延迟积的SD的寄存器传输级实现，用于宽带MIMO通信系统，如IEEE 802.11n，其中需要实例化多个SD内核。基于硬输出SD解释了基本的体系结构考虑和建议的优化，但也适用于软输出SD。相应的VLSI实现结果（硬输出和软输出SD）显示，与文献中报道的其他SD实现相比，区域延迟产品改善了近50%。
Sphere decoding (SD) is a promising means for implementing high-performance data detection in multiple-input multiple-output (MIMO) wireless communication systems. In this paper, we focus on the register transfer level implementation of SD with minimum area-delay product for application in wideband MIMO communication systems, such as IEEE 802.11n, where multiple SD cores need to be instantiated. The basic architectural considerations and the proposed optimizations are explained based on hard-output SD, but are also applicable to soft-output SD. Corresponding VLSI implementation results (for both hard-output and soft-output SD) show an improvement in the area-delay product by almost 50% compared to that of other SD implementations reported in the literature.