Prospective and critical issues of III-V/Ge CMOS on Si platform
Prospective and critical issues of III-V/Ge CMOS on Si platform
复制标题
Si平台上III-V/Ge CMOS的前景和关键问题
DOI:
10.1149/1.3569921
复制
发表时间:
2011
期刊:
影响因子:
--
通讯作者:
S.Takagi and M.Takenaka
中科院分区:
文献类型:
--
作者:
Tetsuya Uchimoto;Toshiyuki Takagi;Xiaodong Deng;Thomas Monnier;Joel Courbon;Thierry Douillard;Varlot Mansenelli;S.Takagi and M.Takenaka
III-V/Ge CMOS on Si platform, realized by heterogeneous integration, is expected to provide a variety of applications from high speed logic CMOS to versatile SoC chips, where various functional devices can be co-integrated. Among them, high speed/low power logic CMOS using III-V/Ge channels are promising device solution for further progress in scaled CMOS. While many critical issues have been well recognized for them, we present possible solutions to break through these difficulties in this paper. Main critical issues of Ge/III-V MOSFETs on Si platform are (1) formation of MIS gate stacks with superior interfacial properties and (2) formation of Ge/III-V channel layers on Si substrates. Ge MOS interfaces with thermally-oxidized GeO2 are promising for the superior interface properties as well as the high inversion-layer mobility. SGOI/GOI structures based on Ge condensation are promising for future ultrathin SGOI/GOI MOSFETs. A wafer bonding technique can be potential solutions of III-V MOSFETs on Si platform. Using this technique, the operation of ultrathin body/ultrathin BOX InGaAs-OI MOSFETs are demonstrated. Also, surface nitridation and surface orientation engineering are shown to be effective in III-V MOS interface control. Finally, novel metal S/D InGaAs MOSFETs utilizing Ni-InGaAs alloys are proposed and demonstrated.