Scalable scheduling architectures for high-performance crossbar-based switches
Scalable scheduling architectures for high-performance crossbar-based switches
复制标题
用于基于交叉开关的高性能交换机的可扩展调度架构
DOI:
10.1109/hpsr.2004.1303441
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发表时间:
2004
期刊:
影响因子:
--
通讯作者:
C. Tsui
中科院分区:
文献类型:
--
作者:
Jing Liu;M. Hamdi;Qingsheng Hu;C. Tsui
This paper presents a novel scalable scheduling architecture for high-performance crossbar-based switches with virtual output queuing (VOQ) scheme. In contrast to traditional switching architectures where the scheduler is implemented by one single centralized scheduling device, the proposed scheduling architecture connects several small scheduling devices in series and the arbitration algorithm is executed in parallel. Thereby the inputs of each single scheduling device establish connections to a group of outputs, by considering both their local transmission requests as well as global output availability information. The advantage of this architecture lies in its ability to implement large schedulers (> 64) with several small scheduling devices as well as in its capability to achieve high-performance scheduling. We first introduce a distributed parallel round robin scheduling algorithm (DPRR) for the proposed architecture. Through the analysis of simulation results on various admissible traffics, it is shown that the performance of DPRR is much better than the performance of other round robin scheduling algorithms commonly used on centralized schedulers. We also prove that under Bernoulli i.i.d. uniform traffic, DPRR achieves 100% throughput. Moreover, we introduce a distributed parallel round robin scheduling algorithm with memory (DPRRM) as an improved version of DPRR to make it stable under any admissible traffic.