Towards in vivo neural decoding
Towards in vivo neural decoding
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DOI：
10.1007/s13534-022-00217-z
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发表时间：
2022-02
影响因子：
4.6
通讯作者：
D. Valencia;A. Alimohammad
中科院分区：
文献类型：
--
作者：
D. Valencia;A. Alimohammad
传统的尖峰分类和马达意图解码算法大多在诸如个人计算机的外部计算设备上实现。高分辨率和高密度电极的创新，可以在单个神经元水平上记录大脑的活动，可能完全消除对棘波分类的需要，同时可能使体内神经解码成为可能。本文探讨了在体内解码的可行性和高效实现，包括有无棘波排序的情况。给出了基于神经网络的可靠电机译码模型的效率，并对候选神经译码方案在排序的单单元活动和未排序的多单元活动上的性能进行了评估。据我们所知，首次设计和实现了一个具有定制指令集体系结构的可编程处理器，用于在标准的180 nm CMOS工艺中执行神经网络操作。据估计，处理器的布局占用了49毫米的硅面积，并从1.8伏的电源中消耗了12毫瓦的电力，这在大脑的组织安全操作范围内。
Conventional spike sorting and motor intention decoding algorithms are mostly implemented on an external computing device, such as a personal computer. The innovation of high-resolution and high-density electrodes to record the brain’s activity at the single neuron level may eliminate the need for spike sorting altogether while potentially enabling in vivo neural decoding. This article explores the feasibility and efficient realization of in vivo decoding, with and without spike sorting. The efficiency of neural network-based models for reliable motor decoding is presented and the performance of candidate neural decoding schemes on sorted single-unit activity and unsorted multi-unit activity are evaluated. A programmable processor with a custom instruction set architecture, for the first time to the best of our knowledge, is designed and implemented for executing neural network operations in a standard 180-nm CMOS process. The processor’s layout is estimated to occupy 49 mmof silicon area and to dissipate 12 mW of power from a 1.8 V supply, which is within the tissue-safe operation of the brain.