A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology
A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology
复制标题
A%2036-V%2049%%20效率%20混合%20充电%20泵%20英寸%20纳米级%20散装%20CMOS%20技术
DOI：
--
复制
发表时间：
2017
影响因子：
5.4
通讯作者：
C. Yang
中科院分区：
文献类型：
--
作者：
Yousr Ismail;Haechang Lee;S. Pamarti;C. Yang
本文介绍了一种混合式电荷泵结构。HCP通过优化混合不同的电荷泵（CP）类型，在电压范围和功率效率之间进行权衡，从而以纳米级CMOS技术实现高电压直流输出，并提高功率效率。在体CMOS工艺中，传统的CP输出仅限于单二极管击穿电压（在65 nm技术节点中<inline-formula><tex-math notation="LaTeX">为$sim 12$</tex-math></inline-formula>V）。为了支持>12 V输出，HCP通过两种技术方法扩展了体CMOS衬底的电压耐受性：双二极管衬底隔离和场氧化物隔离。为了实现这些隔离方法，设计了两个专门的CP单元：一个全nMOS倍压器和一个改进的驱动Dickson型泵。两个HCP设计的例子与相反的电压极性实现在65 nm CMOS工艺，并讨论了他们的测量结果。正电压HCP在20 μ A时达到36 V输出和49%的峰值效率<inline-formula><tex-math notation="LaTeX"> ext{A}$</tex-math></inline-formula>负载电流，占地面积为0.18 mm <inline-formula><tex-math notation="LaTeX">$^{mathrm {mathbf {2}$</tex-math></inline-formula>。该输出电压表示<inline-formula><tex-math notation="LaTeX">3美元 与</tex-math></inline-formula>传统设计相比，该技术的电压范围增加了1倍。
This paper introduces a hybrid charge pump (HCP) architecture. The HCP enables high-voltage dc outputs in a nanometer-scale CMOS technology at improved power efficiency by optimally mixing different charge pump (CP) types that trade off voltage range and power efficiency. Conventional CP outputs in a bulk CMOS process are limited to a single-diode breakdown voltage (<inline-formula> <tex-math notation="LaTeX">$sim 12$ </tex-math></inline-formula> V in a 65-nm technology node). To support >12 V outputs, the HCP extends the voltage tolerance of bulk CMOS substrates via two technology methods: double-diode substrate isolation and field oxide isolation. To enable these isolation methods, two specialized CP cells are devised: an all-nMOS voltage doubler and an improved-drive Dickson-type pump. Two HCP design examples with opposite voltage polarities are implemented in a 65-nm CMOS technology, and their measurement results are discussed. The positive voltage HCP achieves a 36 V output and 49% peak efficiency at a 20-<inline-formula> <tex-math notation="LaTeX">$mu ext{A}$ </tex-math></inline-formula> load current and occupies 0.18 mm<inline-formula> <tex-math notation="LaTeX">$^{mathrm {mathbf {2}}}$ </tex-math></inline-formula> in area. This output voltage represents a <inline-formula> <tex-math notation="LaTeX">$3 imes $ </tex-math></inline-formula> increase in the technology’s voltage range compared to ranges attainable by conventional designs.