High-level power modeling of CPLDs and FPGAs
High-level power modeling of CPLDs and FPGAs
复制标题
CPLD 和 FPGA 的高级功耗建模
DOI：
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
N. Jha
中科院分区：
文献类型：
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作者：
L. Shang;N. Jha
We present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). For simplicity of reference, we simply refer to these devices as FPGAs. First, we capture the relationship between FPGA power dissipation and I/O signal statistics. We then use an adaptive regression method to model the FPGA power consumption. Such a high-level model can be used in the inner loop of a system-level synthesis tool to estimate the power consumed by different FPGA resources for different potential system-level synthesis solutions. It can also be used to verify the power budgets during embedded system design. With our high-level power model, the FPGA power consumption can be obtained very quickly. Experimental results indicate that the average relative error is only 3.1 % compared to low-level FPGA power simulation methods.
