Cycle-based symbolic simulation of gate-level synchronous circuits
Cycle-based symbolic simulation of gate-level synchronous circuits
复制标题
门级同步电路的基于周期的符号仿真
DOI：
10.1109/dac.1999.781347
复制
发表时间：
1999
期刊：
影响因子：
--
通讯作者：
S. Quer
中科院分区：
文献类型：
--
作者：
V. Bertacco;M. Damiani;S. Quer
符号方法通常被认为是验证数字电路的最新技术。然而，由于它们的复杂性和不可预测的运行时行为，它们的潜力目前仅限于中小型电路。逻辑模拟的特权容量，它是很好的可伸缩性，灵活性，它有一个可预测的运行时行为。因此，它是验证大型电路的常见选择。然而，仿真通常只访问状态空间的一小部分。缺陷的发现在很大程度上依赖于测试刺激设计者的专业知识。在本文中，我们考虑一个符号模拟的验证问题的方法。我们的目标是在形式方法和数值方法之间进行权衡，以便并行模拟具有“大量”输入组合和序列的电路。我们展示了更大的容量与符号技术和更好的效率与基于周期的模拟。我们表明，它是可能的，象征性地模拟非常大的轨迹集并行（超过100个符号输入）的最大的ISCAS基准电路，使用96 Mbytes的内存。
Symbolic methods are often considered the state-of-the-art technique for validating digital circuits. Due to their complexity and unpredictable run-time behavior, however, their potential is currently limited to small-to-medium circuits. Logic simulation privileges capacity, it is nicely scalable, flexible, and it has a predictable run-time behavior. For this reason, it is the common choice for validating large circuits. Simulation, however, typically visits only a small fraction of the state space. The discovery of bugs heavily relies on the expertise of the designer of the test stimuli. In this paper we consider a symbolic simulation approach to the validation problem. Our objective is to trade-off between formal and numerical methods in order to simulate a circuit with a "very large number" of input combinations and sequences in parallel. We demonstrate larger capacity with respect to symbolic techniques and better efficiency with respect to cycle-based simulation. We show that it is possible to symbolically simulate very large trace sets in parallel (over 100 symbolic inputs) for the largest ISCAS benchmark circuits, using 96 Mbytes of memory.