Localization of Bugs in Processor Designs Using zamiaCAD Framework
Localization of Bugs in Processor Designs Using zamiaCAD Framework
复制标题
使用 zamiaCAD 框架定位处理器设计中的错误
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
Heinz
中科院分区：
文献类型：
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作者：
A. Tsepurov;Valentin Tihhomirov;M. Jenihhin;J. Raik;Gunter Bartsch;Jorge Hernán Meza Escobar;Heinz
本文提出了一种基于动态覆盖 VHDL 代码项统计分析和静态切片相结合的处理器设计中设计错误（bug）自动定位的方法。该方法考虑了不同 VHDL 代码项的覆盖范围，包括处理器模拟期间的语句、分支和条件，它们共同有助于准确定位错误。通过应用基于静态切片的滤波器，通过使用从处理器设计的语义解析的精细模型中进行信号分配搜索来生成参考图来计算，进一步提高了分析的准确性。本地化方法已集成到高度可扩展的 zamiaCAD RTL 设计框架中。通过将其应用于为基于 FPGA 的测试系统设计的工业处理器 ROBSY 的调试，证明了所提出方法的效率。实验结果评估了一组真实记录的错误案例和原始功能测试的方法。
This paper proposes an approach to automatic localization of design errors (bugs) in processor designs based on combining statistical analysis of dynamically covered VHDL code items and static slicing. The approach considers coverage of different VHDL code items including statements, branches and conditions during processor simulation which together contribute to accurate localization of bugs. The accuracy of analysis is further improved by applying a static slicing based filter calculated by means of reference graph generation using a through-signal-assignment search from the semantically resolved elaborated models of processor designs. The localization approach has been integrated to highly scalable zamiaCAD RTL design framework. The efficiency of the proposed approach is demonstrated by applying it to debugging of an industrial processor ROBSY designed for FPGA-based test systems. The experimental results evaluate the approach for a set of real documented bug cases and the original functional test.