9.2 A 134µW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC
9.2 A 134µW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC
复制标题
具有斩波负 R 和三电平 FIR DAC 的 9.2 A 134μW 24kHz-BW 103.5d8-DR CT ΔΣ 调制器
DOI：
10.1109/isscc19947.2020.9062904
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
Youngcheol Chae
中科院分区：
文献类型：
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作者：
Moonhyung Jang;Changuk Lee;Youngcheol Chae
音频应用需要动态范围（DR）超过100 dB的高分辨率ADC。连续时间Δ-Σ调制器（CTDSM）被广泛用于实现此类ADC，并且对于电池供电的器件需要高能效[1 - 5]。本文提出了一种更有效的，高度线性的CTDSM架构的音频应用。CTDSM的第一个积分器使用斩波负R和三电平FIR DAC，以提高能效。有源RC积分器的非理想性使用积分器的虚拟接地处的负R来补偿，并且负R然后被斩波以在反馈FIR滤波器的陷波频率处去除其1/f噪声。6抽头三电平FIR DAC采用阻性不归零（NRZ）DAC实现，其符号间干扰（ISI）保持在− 120 dB以下。在24kHz带宽下，SNDR为99.4dB，SNR为101dB，DR为103.5dB，SFDR为110.2dB，功耗仅为134 µ W。这对应于186dB的Schreier FoM。
Audio applications require a high-resolution ADC with a dynamic range (DR) of more than 100dB. A continuous-time delta-sigma modulator (CTDSM) is widely used to realize such ADCs and requires high energy efficiency for battery-powered devices [1-5]. This paper presents a more efficient, highly linear CTDSM architecture for audio applications. The first integrator of the CTDSM uses a chopped negative-R in conjunction with a tri-level FIR DAC to increase energy-efficiency. Non-idealities of an active-RC integrator are compensated using a negative-R at the virtual ground of the integrator, and the negative-R is then chopped to remove its 1/f noise at a notch frequency of the feedback FIR filter. A 6-tap, tri-level FIR DAC is realized with a resistive non-return-to-zero (NRZ) DAC whose inter-symbol-interference (ISI) is kept less than −120dB. As a result, this work achieves 99.4dB SNDR, 101dB SNR, 103.5dB DR, and 110.2dB SFDR in a 24kHz bandwidth while consuming only 134\µW. This corresponds to a Schreier FoM of 186dB.