A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.
A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.
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DOI：
10.1109/isscc.2006.1696056
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发表时间：
2006-09
期刊：
影响因子：
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通讯作者：
B. Casper;J. Jaussi;F. O’Mahony;M. Mansuri;K. Canagasaby;J. Kennedy;E. Yeung;R. Mooney
中科院分区：
文献类型：
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作者：
B. Casper;J. Jaussi;F. O’Mahony;M. Mansuri;K. Canagasaby;J. Kennedy;E. Yeung;R. Mooney
未来的微处理器平台将需要I/O的系统级优化，以最小化成本并最大化总带宽。关键参数，如硅面积，功率，可测性和片外互连质量必须得到适当的平衡，以最大限度地提高I/O性能与成本比。例如，在时钟质量和均衡器效率之间存在基本的权衡[1]。产生精确的RX和TX时钟以及灵敏的RX可能会影响某些电路的功耗和面积，但它可以允许使用简单的低功耗线性均衡器来最大限度地降低整体链路功耗。此外，通过限制近端串扰和短截背板（BP）过孔长度，这些均衡器将变得更加有效。为了证明这一系统级的优化工作，我们已经开发了一个20 Gb/s的转发时钟I/O系统，用于广泛的并行链路，面积小，功耗低。
Future microprocessor platforms will require system-level optimization of the I/O to minimize cost and maximize aggregate bandwidth. Critical parameters such as silicon area, power, testability, and off-chip interconnect quality must be properly balanced to maximize the I/O performance versus cost ratio. For example, there is a fundamental tradeoff between clock quality and equalizer effectiveness [1]. Producing precision RX and TX clocks and a sensitive RX may impact the power and area of some circuits, but it could allow the use of simple, low-power linear equalizers to minimize the overall link power. Additionally, these equalizers will become much more effective by limiting near-end crosstalk and stubbed backplane (BP) via length. To demonstrate this system-level optimization effort, we have developed a 20Gb/s forwarded clock I/O system intended for a wide parallel link with small area and low power.