Applying the small-world network to routing structure of FPGAs
Applying the small-world network to routing structure of FPGAs
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DOI：
10.1109/fpl.2005.1515700
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发表时间：
2005-10
期刊：
影响因子：
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通讯作者：
Hisashi Tsukiashi;M. Iida;T. Sueyoshi
中科院分区：
文献类型：
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作者：
Hisashi Tsukiashi;M. Iida;T. Sueyoshi
随着新工艺技术的发展，可编程逻辑的集成度和工作频率有了显著提高。然而，对于深亚微米工艺，延迟、可靠性、成本和功耗往往由互连决定。在传统的可编程逻辑中，减少关键路径上的开关数量很重要，因为布线延迟比开关延迟小得多。然而，为了降低关键路径延迟，对于深亚微米工艺也有必要考虑布线延迟。本文提出一种利用小世界网络结构进行可编程逻辑互连的新型布线结构。本文证明关键路径延迟能够降低。基于评估结果，作者表明当使用小世界网络结构时，关键路径延迟最多可降低15%，布线资源量最多可减少23%。
The degree of integration and the operating frequency of programmable logic have improved dramatically with the development of new process technologies. However, for the deep sub-micron processes, the delay, reliability, cost, and power tend to be determined by interconnections. In conventional programmable logic, reducing the number of switches on a critical path is important because the wiring delay is considerably smaller than the switch delay. However, to achieve a decrease in the critical path delay it is also necessary to consider the wiring delay for the deep sub-micron processes. This paper proposes a novel routing structure using a small-world network structure for the interconnection of programmable logic. This paper demonstrates that the critical path delay can be reduced. Based on the results of an evaluation, the authors show that the critical path delay can be reduced by a maximum of 15% and the amount of routing resources can be reduced by a maximum of 23% when using the small-world network structure.