Pixel noise suppression via SoC management of tapered reset in a 1920 x 1080 CMOS image sensor
Pixel noise suppression via SoC management of tapered reset in a 1920 x 1080 CMOS image sensor
复制标题
DOI：
10.1109/jssc.2005.858480
复制
发表时间：
2005-12-01
影响因子：
5.4
通讯作者：
Standley, D
中科院分区：
文献类型：
--
作者：
Kozlowski, LJ;Rossi, G;Standley, D
相关双采样广泛应用于成像阵列中，以消除 CCD 感应电容或 CMOS 传感器光电二极管在信号积分和读出后复位时产生的噪声。相反，我们使用 SoC 实现进行渐进式复位来抑制光电二极管 kTC 噪声；支持 SoC 组件包括反馈放大器（其元件分布在像素和列缓冲器中）、锥形复位时钟波形和复位时序发生器。该重置方法不会膨胀像素区域、强制处理相关的重置和信号值或需要额外的存储器。理论分析与实验结果一起呈现。集成在 0.25-μm CMOS 中具有 5μm x 5μm 像素的 1920 x 1080 成像仪中，测得的 5.5-fF 探测器电容的随机噪声与 8 e- 至 225 MHz 视频速率相似，在 60 Hz 和 72 Hz 帧速率下图像滞后 = 52 dB。
Correlated double sampling is widely used in imaging arrays to eliminate noise generated when a CCD's sense capacitance or a CMOS sensor's photodiode is reset after signal integration and readout. Instead, we suppress photodiode kTC noise using a SoC implementation for progressive reset; supporting SoC components include a feedback amplifier having elements distributed amongst the pixel and column buffer, a tapered reset clock waveform, and reset timing generator. The reset method does not swell pixel area, compel processing of the correlated reset and signal values, or require additional memory. Theoretical analysis is presented along with experimental results. Integrated in a 1920 by 1080 imager having 5 mu m by 5 mu m pixels in 0.25-mu m CMOS, measured random noise for 5.5-fF detector capacitance is similar to 8 e- to 225 MHz video rate with image lag = 52 dB at 60 Hz and 72 Hz frame rate.