VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling

VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
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DOI:
10.1145/2068716.2068718
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发表时间:
2011-12
期刊:
ACM Trans. Reconfigurable Technol. Syst.
影响因子:
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通讯作者:
J. Luu;Ian Kuon;P. Jamieson;T. Campbell;A. Ye;W. Fang;K. Kent;Jonathan Rose
J. Luu;Ian Kuon;P. Jamieson;T. Campbell;A. Ye;W. Fang;K. Kent;Jonathan Rose
中科院分区:
其他
文献类型:
--
作者:
J. Luu;Ian Kuon;P. Jamieson;T. Campbell;A. Ye;W. Fang;K. Kent;Jonathan Rose

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VPR工具集已广泛用于FPGA架构和CAD研究,但在过去十年中没有发展。本文介绍并演示了新版本工具集的使用,该工具集包括四项新功能:首先,它支持广泛的单驱动器路由架构,与以前的多驱动器方法(现在大多数销售的FPGA都采用这种方法)相比,单驱动器路由架构具有上级架构和电气特性。其次,它现在可以建模,用于放置和布线硬逻辑块的异构选择。这是一个关键(但不是最后)的一步,朝着包括块,如内存和乘法器。第三,我们为不同工艺技术的各种架构提供了优化的电气模型,包括每种架构的面积延迟权衡。最后,为了保持健壮性并支持未来的开发,该版本包括一组软件回归测试。为了说明新功能的使用,我们探讨了几个架构问题:FPGA面积效率与逻辑块粒度,单驱动器路由的影响,以及简单地使用异质性来探索硬乘法器对布线轨道数的影响。
The VPR toolset has been widely used in FPGA architecture and CAD research, but has not evolved over the past decade. This article describes and illustrates the use of a new version of the toolset that includes four new features: first, it supports a broad range of single-driver routing architectures, which have superior architectural and electrical properties over the prior multidriver approach (and which is now employed in the majority of FPGAs sold). Second, it can now model, for placement and routing a heterogeneous selection of hard logic blocks. This is a key (but not final) step toward the incluion of blocks such as memory and multipliers. Third, we provide optimized electrical models for a wide range of architectures in different process technologies, including a range of area-delay trade-offs for each single architecture. Finally, to maintain robustness and support future development the release includes a set of regression tests for the software. To illustrate the use of the new features, we explore several architectural issues: the FPGA area efficiency versus logic block granularity, the effect of single-driver routing, and a simple use of the heterogeneity to explore the impact of hard multipliers on wiring track count.