Low-Temperature Formation of High-Quality $ \hbox{GeO}_{2}$ Interlayer for High-$\kappa$ Gate Dielectrics/Ge by Electron-Cyclotron-Resonance Plasma Techniques
Low-Temperature Formation of High-Quality $ \hbox{GeO}_{2}$ Interlayer for High-$\kappa$ Gate Dielectrics/Ge by Electron-Cyclotron-Resonance Plasma Techniques
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DOI：
10.1109/ted.2009.2035030
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发表时间：
2010
影响因子：
3.1
通讯作者：
Y. Fukuda;Y. Yazaki;Y. Otani;T. Sato;H. Toyota;T. Ono
中科院分区：
文献类型：
--
作者：
Y. Fukuda;Y. Yazaki;Y. Otani;T. Sato;H. Toyota;T. Ono
我们采用电子回旋共振等离子体氧化溅射技术，在p型Ge衬底上制备了Al_2O_3/GeO_2栅介质层。计算结果表明，GeO2/Ge界面的禁带中界面态密度为4.5×1010 cm-2·eV-1。在电容-电压测量中观察到的磁滞减小到50 mV，当栅偏压从累加扫描到反转再回到累加时，或者在从反相到累加的单次虚拟扫描之后，表明引起磁滞的体氧化物陷阱被注入的空穴去活的可能性。通过内部光电子能谱测量，得到GeO2的带隙为4.7 eV。GeO2/Ge界面的导带和价带偏移量是中等对称和较大的，分别为1.8 eV和2.2 eV。这些有希望的结果表明，低温等离子体生长的GeO2是高介电常数介质和Ge之间的合适的过渡层。
We have fabricated an Al2O3/GeO2 gate-dielectric stack on p-type Ge by electron-cyclotron-resonance plasma oxidation and sputtering without external substrate heating. We show that the midgap interface state density at the GeO2/Ge interface is 4.5 × 1010 cm-2 · eV-1. The hysteresis observed in capacitance-voltage measurements is reduced to 50 mV when the gate bias is swept from accumulation to inversion and back to accumulation or after a single dummy sweep from inversion to accumulation, indicating the possibility that the bulk oxide traps causing the hysteresis are deactivated by the injected holes. The band gap of GeO2 was determined by internal photoemission measurements to be 4.7 eV. The conduction- and valence-band offsets at the GeO2/Ge interface are moderately symmetric and large with values of 1.8 and 2.2 eV, respectively. These promising results suggest that low-temperature plasma-grown GeO2 is a suitable interlayer between high-dielectric-constant dielectrics and Ge.