A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch-猫眼课题宝

DOI：

10.1109/vlsit.2010.5556135

发表时间：

2010-06

期刊：

2010 Symposium on VLSI Technology

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中科院分区：

其他

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作者：

V. Basker;T. Standaert;H. Kawasaki;Chun-Chen Yeh;Kingsuk Maitra;T. Yamashita;J. Faltermeier;H. Adhikari;Hemanth Jagannathan;Wang Junli;Hiroshi Sunamura;S. Kanakasabapathy;S. Schmitz;Jason E. Cummings;A. Inada;C. -. Lin;P. Kulkarni;Yu Zhu;J. Kuss;Toyoji Yamamoto;Arvind Kumar;Jeremy A. Wahl;A. Yagishita;Lisa F. Edge;Ryoung-han Kim;E. Mclellan;Steven J. Holmes;R. Johnson;T. Levin;James J. Demarest;Masami Hane;Mariko Takayanagi;Matt Colburn;Vamsi k. Paruchuri;R. Miller;Huiming Bu;Bruce B. Doris;D. Mcherron;Effendi Leobandung;J. O’Neill

我们使用光学光刻技术展示了迄今为止报道的最小的FinFET静态随机存取存储器单元尺寸为0.063微米。该单元首次使用最先进的300 mm工具集制造，接触栅距(CPP)调整到80 nm，鳍片间距调整到40 nm。一种独特的图案化方案采用了双曝光、双腐蚀(DE2)侧壁图像转移(SIT)工艺来形成鳍片。该方案还在SRAM单元中形成差分鳍间距，其中外延膜用于仅合并紧密间距的器件。外延膜还用于器件的共形掺杂，显著降低了器件的外阻。其他功能包括栅极优先金属栅堆栈和具有25 nm栅长的晶体管，具有出色的短沟道控制。

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

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