Efficiently Exploiting Low Activity Factors to Accelerate RTL Simulation
Efficiently Exploiting Low Activity Factors to Accelerate RTL Simulation
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有效利用低活动因子来加速 RTL 仿真
DOI：
10.1109/dac18072.2020.9218632
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
D. Donofrio
中科院分区：
文献类型：
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作者：
S. Beamer;D. Donofrio
硬件仿真是设计的关键工具，但是其慢速瓶颈通常会瓶颈整个设计过程。尽管数字设计中的大多数信号很少发生变化，但是大多数领先的模拟器仍然模拟每个周期的整个设计。跟踪哪些信号没有变化，因此可以重复使用通常会引入太多的开销，无法提供实用的加速。在这项工作中，我们探索了有效检测出重复使用机会的挑战，并且我们展示了实用的技术来利用它们。得益于我们新颖的无环分区算法和其他优化，我们生成的模拟器的开源和工业最先进的模拟器均优于开源和工业最先进的模拟器。
Hardware simulation is a critical tool for design, but its slow speed often bottlenecks the entire design process. Although most signals in a digital design rarely change, most leading simulators still simulate the entirety of the design every cycle. Tracking which signals are unchanged and can thus be reused typically introduces too much overhead to deliver a practical speedup.In this work, we explore the challenge of efficiently detecting opportunities for reuse, and we demonstrate practical techniques to profitably exploit them. Thanks to our novel acyclic partitioning algorithm and other optimizations, our generated simulators outperform open-source and industrial state-of-the-art simulators.