Digital ground bounce reduction by supply current shaping and clock frequency Modulation
Digital ground bounce reduction by supply current shaping and clock frequency Modulation
复制标题
通过电源电流整形和时钟频率调制减少数字地弹
DOI：
10.1109/tcad.2004.839471
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发表时间：
2005
影响因子：
2.9
通讯作者：
H. Man
中科院分区：
文献类型：
--
作者：
M. Badaroglu;P. Wambacq;G. V. D. Plas;S. Donnay;G. Gielen;H. Man
在同步时钟分配网络中，数字电路在时钟边缘同时切换；因此，由于电源电流的尖峰，它们产生地面反弹。我们展示了两种方法的有效组合，基于塑造电源电流来减少地面反弹：1)向同步时钟网络引入有意的倾斜，2)系统时钟的频率调制。前一种技术通过扩展同时开关活动来减小电源电流的时域峰值和频谱功率。后一种技术通过将这种功率分散到时钟谐波周围形成的侧瓣中，而不改变电源电流的频谱功率，从而减少了时钟谐波中包含的功率。我们还描述了一个分析框架来分析电源电流的周期性变化对地面反射电压的影响。在块型衬底上采用0.18-/spl μ m 1.8 v CMOS工艺的40k门电路的仿真结果表明，在电路谐振处，地弹跳谱的频谱峰值降低了约26 dB，在时域内，地弹跳的峰对峰和RMS值分别降低了3.04/spl倍和2.64/spl倍。这两种技术被认为是CMOS技术中数字低噪声设计发展的良好候选者。
In a synchronous clock-distribution network, digital circuits switch simultaneously on the clock edge; therefore, they generate ground bounce due to sharp peaks of the supply current. We demonstrate an effective combination of two methodologies for ground-bounce reduction based on shaping the supply current: 1) introducing intentional skews to the synchronous clock network and 2) frequency modulation of the system clock. The former technique reduces the time-domain peaks as well as the spectral power of the supply current by spreading the simultaneous switching activities. The latter technique reduces the power contained in the clock harmonics by spreading this power into the side lobes formed around the clock harmonics without any change in the spectral power of the supply current. We also describe an analytical framework to analyze the impact of cycle-to-cycle variations of the supply current on the ground-bounce voltage. Simulation results for a 40K-gates circuit in a 0.18-/spl mu/m 1.8-V CMOS process on a bulk-type substrate show around 26 dB reduction in the spectral peaks of the ground-bounce spectrum at the circuit resonance and factors of 3.04/spl times/ and 2.64/spl times/ reduction in the peak-to-peak and RMS values, respectively, of the ground bounce in the time domain when these two techniques are combined. These two techniques are believed to be good candidates for the development of digital low-noise designs in CMOS technologies.