Technology for sub-50nm DRAM and NAND flash manufacturing
Technology for sub-50nm DRAM and NAND flash manufacturing
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DOI：
10.1109/iedm.2005.1609340
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发表时间：
2005-12
期刊：
影响因子：
--
通讯作者：
Kinam Kim
中科院分区：
文献类型：
--
作者：
Kinam Kim
本文讨论了存储技术是否可以继续进步到 50 纳米以下节点，尤其是 DRAM 和 NAND 闪存。首先，根据 DRAM 和 NAND 闪存固有的操作原理，解决了缩小技术的障碍。然后，介绍了技术解决方案的细节并检验了其可制造性。超过30nm节点，除了新材料和结构技术的发展外，预计逻辑和存储阵列都需要3维晶体管方案
This paper discusses whether memory technologies can continue advances beyond sub-50nm node especially for DRAM and NAND flash memories. First, the barriers to shrink technology are addressed for DRAM and NAND flash memories, depending on their inherent operation principles. Then, details of technology solutions are introduced and its manufacturability is examined. Beyond 30nm node, It is expected that 3-dimensional transistor scheme is needed for both logic and memory array in addition to the development of new materials and structural technologies