Design of Memory Sub-System in H.264/AVC Decoder
Design of Memory Sub-System in H.264/AVC Decoder
复制标题
H.264/AVC解码器存储子系统设计
DOI：
10.1109/icce.2007.341382
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
Tihao Chiang
中科院分区：
文献类型：
--
作者：
Chih;Chang;Wen;W. Hwang;Tihao Chiang
在本文中，我们提出了一个H.264/AVC解码器的高配置文件和4级设计的存储器子系统。我们的设计采用了同步缓冲区作为预缓存缓冲区。我们调查的效率DRAM访问和功耗时，缓冲区的设计在不同的粒度。统计结果表明，较大的块大小的粒度具有更高的存储效率，更少的访问周期和功耗。然而，8 × 8块大小的粒度在成本、效率、功率和实时要求之间提供了更好的折衷。
In this paper, we present the memory sub-system of a H.264/AVC decoder designed for high profile and level 4. Our design incorporates a synchronization buffer as a pre-cache buffer. We investigate the efficiency of DRAM access and power dissipation when the buffer is designed at different granularities. Statistical results show that the granularity of larger block size has higher memory efficiency, less access cycles and power dissipation. However, the granularity of 8times8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.