Leave the cache hierarchy operation as it is: A new persistent memory accelerating approach
Leave the cache hierarchy operation as it is: A new persistent memory accelerating approach
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DOI：
10.1145/3061639.3062272
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发表时间：
2017-06
期刊：
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通讯作者：
Chun-Hao Lai;Jishen Zhao;Chia-Lin Yang
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文献类型：
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作者：
Chun-Hao Lai;Jishen Zhao;Chia-Lin Yang
持续的内存将NVRAM放置在内存总线上，可快速访问持久数据。然而，维持NVRAM数据持久性会引起许多挑战。大多数提出的计划要么会产生大量的性能开销，要么需要对现有体系结构进行重大修改。我们提出了一个持久的内存加速器设计，该设计可以通过硬件来保证NVRAM数据持久性，但仍使高速缓存层次结构和内存控制器操作未经改变。非挥发性事务缓存可与缓存层次结构并排保持数据更新的替代版本，并铺平了新的持久路径，而不会影响原始处理器执行路径。结果，我们的设计实现了靠近持久保证的表现。
Persistent memory places NVRAM on the memory bus, offering fast access to persistent data. Yet maintaining NVRAM data persistence raises a host of challenges. Most proposed schemes either incur much performance overhead or require substantial modifications to existing architectures. We propose a persistent memory accelerator design, which guarantees NVRAM data persistence by hardware yet leaving cache hierarchy and memory controller operations unaltered. A nonvolatile transaction cache keeps an alternative version of data updates side-by-side with the cache hierarchy and paves a new persistent path without affecting original processor execution path. As a result, our design achieves the performance close to the one without persistence guarantee.