A novel FPGA logic block for improved arithmetic performance
A novel FPGA logic block for improved arithmetic performance
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一种新颖的 FPGA 逻辑块，可提高算术性能
DOI：
10.1145/1344671.1344698
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
P. Ienne
中科院分区：
文献类型：
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作者：
H. Parandeh;P. Brisk;P. Ienne
为了提高运算电路的FPGA性能，本文提出了一种新的FPGA逻辑单元结构，包括一个6：2压缩器。新的单元具有额外的快速进位链，连接相邻的压缩器，可以在没有全局路由网络的情况下进行本地路由。与之前用于二进制和三进制加法的进位链不同，新单元使用的进位链仅跨越2个逻辑块，这显著改善了映射到FPGA上的多输入加法运算的延迟。用新的压缩器结构扩充传统FPGA逻辑单元所产生的延迟和面积开销是最小的。使用这种新单元，我们观察到与使用三进制加法器合成的加法器树相比，组合延迟的平均加速为1.41倍
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed locally without the global routing network. Unlike previous carry-chains for binary and ternary addition, the carry chain used by the new cell only spans 2 logic blocks, which significantly improves the delay of multi-input addition operations mapped onto the FPGA. The delay and area overhead that arises from augmenting a traditional FPGA logic cell with the new compressor structure is minimal. Using this new cell, we observed an average speedup in combinational delay of 1.41x compared to adder trees synthesized using ternary adders