A Low-Power Configurable Neural Recording System for Epileptic Seizure Detection
A Low-Power Configurable Neural Recording System for Epileptic Seizure Detection
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DOI：
10.1109/tbcas.2012.2228857
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发表时间：
2013-08-01
影响因子：
5.1
通讯作者：
Sanchez-Sinencio, Edgar
中科院分区：
文献类型：
--
作者：
Qian, Chengliang;Shi, Jess;Sanchez-Sinencio, Edgar
本文介绍了一种低功耗可配置的神经记录系统，能够捕获和数字化神经动作电位（AP）和快速纹波（FR）信号。它演示了通过FR记录检测癫痫发作的功能。该系统采用固定增益、可变带宽（BW）前端电路和带宽和功耗可扩展的Σ-Δ型ADC。该ADC采用2阶单位Σ-Δ调制器（SDM），后跟一个低功耗抽取滤波器。在抽取滤波器的设计中，提出了sinc（3）滤波器的直接脉冲响应实现和IIR滤波器中的8周期数据流水线，以提高功耗和面积效率。在测量中，前端表现出39.6 dB的直流增益，0.8 Hz至5.2 kHz的带宽，5.86 mu Vrms的输入参考噪声，2.4 mu W的功耗在AP模式，而显示38.5 dB的直流增益，250至486 Hz的带宽，2.48 mu Vrms的噪声，4.5 mu W的功耗在FR模式。AP和FR模式的噪声效率因子（NEF）分别为2.93和7.6。在77 dB动态范围（DR）下，ADC的峰值SNR和SNDR分别为75.9 dB和67 dB，而AP模式下的功耗为2.75 mW。FR模式下，该器件实现78 dB DR、76.2 dB峰值SNR、73.2 dB峰值SNDR和588 μ W功耗。模拟和数字电源电压均为2.8 V。该芯片采用标准的0.6 μ m CMOS工艺制造。模具尺寸为11.25 mm（2）。
This paper describes a low-power configurable neural recording system capable of capturing and digitizing both neural action-potential (AP) and fast-ripple (FR) signals. It demonstrates the functionality of epileptic seizure detection through FR recording. This system features a fixed-gain, variable-bandwidth (BW) front-end circuit and a sigma-delta ADC with scalable bandwidth and power consumption. The ADC employs a 2nd-order single-bit sigma-delta modulator (SDM) followed by a low-power decimation filter. Direct impulse-response implementation of a sinc(3) filter and 8-cycle data pipelining in an IIR filter are proposed for the decimation filter design to improve the power and area efficiency. In measurements, the front end exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of BW, 5.86-mu Vrms input-referred noise, and 2.4-mu W power consumption in AP mode, while showing 38.5-dB DC gain, 250 to 486 Hz of BW, 2.48-mu Vrms noise, and 4.5-mu W power consumption in FR mode. The noise efficiency factor (NEF) is 2.93 and 7.6 for the AP and FR modes, respectively. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-mu W power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-mu m CMOS process. The die size is 11.25 mm(2).