The effectiveness of delay and IDDT tests in detecting resistive open defects for nanometer CMOS adder circuits
The effectiveness of delay and IDDT tests in detecting resistive open defects for nanometer CMOS adder circuits
复制标题
延迟和 IDDT 测试在检测纳米 CMOS 加法器电路电阻开路缺陷方面的有效性
DOI：
10.1109/idt.2011.6123101
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
A. Kayssi
中科院分区：
文献类型：
--
作者：
L. Hamieh;N. Mehdi;Ghazalah Omeirat;A. Chehab;A. Kayssi
In this paper we evaluate the effectiveness of different testing schemes in detecting resistive-open defects in adder circuits implemented using different CMOS technologies (45 nm, 32 nm, 22 nm and 16 nm). We assess the detection capabilities of four testing techniques taking into consideration the wide process variations associated with the different nanometer technologies. The first three techniques are based on the transient supply current, iDDT, and the fourth technique is based on delay testing. The first iDDT method uses the RMS value of the wavelet transform of the transient power supply or ground currents. The second one uses the normalized RMS value of the wavelet transform. The third one uses the peak value of iDDT. The fourth technique measures the primary input-to-output delay. The experimental results show that the delay test is the most effective among all tests. The iDDT test with normalized RMS value of wavelet transform comes second. The other two tests were less effective than the first two, especially in the case of smaller technologies (22 and 16 nm).
