Novel high growth rate processes for depositing poly-SiGe structural layers at CMOS compatible temperatures
Novel high growth rate processes for depositing poly-SiGe structural layers at CMOS compatible temperatures
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用于在 CMOS 兼容温度下沉积多晶硅Ge结构层的新型高生长速率工艺
DOI：
10.1109/mems.2004.1290686
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
A. Witvrouw
中科院分区：
文献类型：
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作者：
A. Mehta;M. Gromova;C. Rusu;R. Olivier;K. Baert;C. van Hoof;A. Witvrouw
本文介绍了两种在CMOS兼容温度（/spl les/450/spl deg/C）下沉积多晶SiGe薄膜的新工艺。研究了一系列沉积温度，以确保与不同CMOS世代的兼容性。虽然多层工艺研究的温度范围在420-450/spl deg/C之间，但微晶SiGe沉积已经可以在低至300/spl deg/C的温度下进行。这些膜被优化以获得适合于MEMS结构层的低应力和应力梯度值。SiGe-Al接触电阻率低至10/sup-7/spl Ω/.cm/sup 2/，薄膜电阻率低至1 m/spl Ω/.cm。
This paper describes two novel processes for depositing poly-SiGe films at CMOS-compatible temperatures (/spl les/450/spl deg/C). A range of deposition temperatures is investigated to ensure compatibility with different CMOS generations. While the multilayer process investigates temperatures ranging between 420-450/spl deg/C, the microcrystalline SiGe deposition has been made possible at temperatures as low as 300/spl deg/C. These films are optimized to obtain low stress and stress gradient values suitable for MEMS structural layers. Low SiGe-Al contact resistivity on the order of 10/sup -7/ /spl Omega/.cm/sup 2/ and film resistivity as low as 1 m/spl Omega/.cm were achieved as well.